1. Field of the Invention
The present invention relates to a method of manufacture of a semiconductor device, and more particularly to a method of manufacture including a dummy pattern for planarizing a global step portion of a semiconductor device.
2. Description of the Related Art
In recent years, greater and greater numbers of active elements have been formed on a single substrate in manufacturing more highly integrated circuits. In the initial steps of the manufacturing process each active element is formed separately. The individual elements are interconnected during subsequent steps of the manufacturing process in order to obtain a desired circuit function. Accordingly, MOS and bipolar VLSI and ULSI devices typically have multilevel interconnection structures for achieving the desired element interconnection.
In such an interconnecting structure, the increase in the number of layers also increases the roughness of the top layer topography. For example, when manufacturing a semiconductor wafer having at least two interconnecting metal layers, a first insulating interlayer is formed about a first metal layer (which in turn, has been formed above other layers, such as a plurality of oxide layers, a polycrystalline silicon conductive layer, and a semiconductor wafer). A via hole is then formed in the insulating interlayer to permit the second metal layer to contact the first metal layer. Because the topography below the first insulating interlayer is uneven, the surface of the first insulating interlayer is also uneven. When the second metal layer is directly formed on this first insulating interlayer, the second metal layer is subject to fractures and thinning due to the uneven topography of the first insulating interlayer. These metallization defects degrade the yield and reliability of the semiconductor device. Accordingly, in multilevel metal interconnection, planarization of the insulating interlayer is necessary prior to forming the via holes or second metal layer.
Dynamic random access memories (DRAMs) generally consist of a cell array region for storing data, each cell having a single transistor and a single capacitor, and a peripheral circuit region for storing or transmitting data to each cell by driving the cell array. In the production of VLSI and ULSI DRAMs, the production of VLSI and techniques for providing sufficient capacitance for the cell capacitor have been developed which include forming a stacked storage electrode of the cell capacitor or by increasing the height of the storage electrode. The more densely packed the semiconductor device is, the greater the number of steps of the patterns formed in the cell array region. In addition, the vertical step differential between the surfaces of the cell array region and the peripheral circuit region is increased.
The simplest method for planarizing the semiconductor wafer having steps is to deposit CVD-SiO.sub.2 thicker than the steps to be coated. However, since a thicker insulating layer increases the depth of the via between the first and second metal layers, this method is impractical. Moreover, as the spacing between the first metal layers is narrowed, voids may be formed in the insulating layer when the SiO.sub.2 is deposited with conventional chemical vapor deposition (CVD). Another method has been disclosed wherein, after depositing an insulating interlayer as described above, a sacrificial resist layer is formed and etched back, thereby planarizing the insulating interlayer. However, not only are the etch-back processing conditions difficult to adjust, but an additional insulating layer must be deposited to complete the process. Thus, the process becomes overly complicated.
An alternative planarization method has been proposed wherein an insulating layer having a reflow characteristic is formed in place of the common CVD-SiO.sub.2, and then heat-treated, thereby planarizing the insulating layer. For example, in "Silicon Processing for the VLSI Era" (S. Wolf, Vol. 2, 1990, pp. 208 and 209), a borophosphosilicate glass (BPSG) layer having 4.8 wt % boron and 4.6 wt % phosphorous is formed and then annealed at 900.degree. C. for 30 minutes in a nitrogen ambient, thereby obtaining an insulating layer having a nearly planar surface. Other proposed planarization methods include rapid thermal processing, which also maintains a shallow junction region rapid thermal processing, or a reflow method of BPSG using, e.g., a CVD apparatus which can simultaneously perform deposition and reflow. In addition, Japanese Patent Publication No. 3-212958 (Korean Patent Publication No. 91-15046) discloses a method for enhancing the planarization by successively repeating the formation and heat-treating of the BPSG layer.
FIGS. 1 and 2 are schematic diagrams showing a conventional BPSG reflow technique. Referring to FIG. 1, a conductive layer is formed by depositing a metal or polysilicon on a semiconductor substrate 100, and is then patterned and etched to form a first wiring pattern 1. Thereafter, a BPSG layer 2 is formed on semiconductor substrate 100 having pattern 1 thereon. Referring to FIG. 2, the reflow of BPSG layer 2 is then carried out by heat treatment at a temperature of 900.degree. C. for 30 to 60 minutes to obtain a nearly planar surface.
However, utilizing the conventional BPSG reflow method described above, if the step structure consists of both closed steps in densely patterned regions and global steps between regions or where patterns are more widely spaced, the degree of planarization at the global step is reduced. This lack of uniform planarization thus degrades the reliability and yield of the semiconductor device, since notching or discontinuities in the metal wiring may occur during the subsequent metal wiring process.
FIG. 3 illustrates the uneven surface of the BPSG layer formed at the global step after reflow. Here, a reference numeral 200 designates a semiconductor substrate; 21 is a pattern; 22 is a BPSG layer; I.sub.1 is a closed step portion; I.sub.2 is a global step portion; x.sub.1 is the spacing between patterns in the closed step portion; x.sub.2 is the spacing between patterns in the global step portion; t.sub.2 is the difference between the peak height of BPSG layer 22 and the height of BPSG layer 22 in the global step portion; and t.sub.3 is the thickness of BPSG layer 22 formed on pattern 21. As can be seen in FIG. 3, after executing the reflow heat-treatment, the planarization of the BPSG layer in the closed step portion having narrow spacing between patterns is relatively good, but that of the global step portion having distant spacing between patterns is inferior.
As disclosed in the above-mentioned Japanese Patent publication, the unevenness of the global step portion is not improved by repeating the BPSG coating and heat-treatment.